The memory is a device for the computer to save data and commands. Please refer to FIG. 1, which is a circuit diagram of the memory bit-line voltage generator in the prior art. The circuit includes a voltage regulator 11 and a switch unit 12. The circuit is used for providing the voltage to a memory array 13, wherein the voltage regulator 11 is connected to the switch unit 12, and the switch unit 12 is connected to the memory array 13. The voltage regulator 11 includes an operational amplifier 111, a pull high transistor Mph and resisters R1, R2. The inverting input terminal of the operational amplifier receives a reference voltage Vref, the noninverting input terminal thereof is connected between the resistors R1, R2, and the output terminal thereof is connected to the gate of the pull high transistor Mph. The source of the pull high transistor receives a voltage Vpp, and the drain thereof is connected to a first terminal of the resistor R1. A first terminal of the resistor R2 is connected to a second terminal of the resistor R1, and a second terminal thereof is connected to ground.
The switch unit 12 includes a switch transistor Msw and a clamp transistor Mclamp. The gate of the switch transistor Msw receives a control signal ø, the drain thereof receives the voltage Vpp, and the source thereof is connected to the drain of the clamp transistor Mclamp. The gate of the clamp transistor Mclamp is connected to the drain of the pull high transistor Mph, and the source thereof is connected to the bit-line of the memory array 13. A parasitic capacitor Cp exists between the gate and the source of the clamp transistor Mclamp. The parasitic capacitor Cp is precharged via the pull high transistor Mph and discharged via the resistors R1, R2. The memory array 13 is composed of a plurality of transistors 131, wherein the gate of each transistor 131 receives a high voltage Vh respectively.
The pull high transistor Mph, the switch transistor Msw, the clamp transistor Mclamp and the transistor 131 described above are MOSFETs.
Please refer to FIG. 2, which is a waveform diagram of respective nodes in the circuit of FIG. 1, wherein Node NB is located between the pull high transistor Mph and the clamp transistor Mclamp, Node NC is located between the switch transistor Msw and the clamp transistor Mclamp, and Node NC is located between the clamp transistor Mclamp and the memory array 13. When the control signal ø is high, the switch transistor Msw is turned on and the voltage V(ND) rises from 0V to 7V, so the charge in the parasitic capacitor Cp must be discharged 7V via the resistors R1, R2. Therefore, when the switch transistor Msw is turned on, an overshoot occurs on the voltage V(NB). However, because the conventional voltage regulator 11 is discharged only via a string of resistors R1, R2, the discharge time thereof is very long. Besides, due to the excessively long finite settling time of the conventional voltage regulator 11, the parasitic capacitor Cp will be over discharged. The above-mentioned issues will cause the voltage V(ND) provided to the bit-line of the memory array 13 to be unstable.
In order to overcome the drawbacks in the prior art, a low couple effect bit-line voltage generator is provided. The particular design in the present invention not only solves the problems described above, but also is easy to be implemented. Thus, the present invention has the utility for the industry.